In a control chip of a PSR (Primary-Side Regulation) flyback power supply, the output voltage is commonly regulated through regulation modes with static error, such as PWM (Pulse Width Modulation), PFM (Pulse Frequency Modulation). In a constant voltage loop, the amplified error value between the output voltage and the reference voltage is adopted to represent the magnitude of the output load (power), and is taken as the loop control voltage to regulate the input power, and to ensure the output voltage to be constant within a certain accuracy range. The amplified error value VEA can be represented by the formula VEA=VREF+AV (VREF−VFB), wherein, VREF is a reference voltage; AV is a gain of the error amplifier; VFB is a sampling value of the output voltage. The relationship between VFB and the output voltage is that: VFB=KSMP×VOUT, wherein, KSMP is a sampling ratio. On the other hand, when the transformer operates in DCM (Discontinuous Current Mode), the relationship between the input power and the output power of the power converter is that:
                    1        2            ⁢              L        m            ×                        (                                    V              IPK                                      R              CS                                )                2            ×              f        sw            ×      η        =                  V        OUT            ×              I        OUT              ,
wherein, LM is the inductance of the primary side of the transformer; RCS is the resistance of the current detection resistor of the primary side of the transformer; VIPK is the voltage peak of the resistor RCS; fSW is the switching frequency of the power transistor of the primary side of the transformer; η is the conversion efficiency of the power supply. In addition, the relationship between the VIPK and VEA in PWM is that: VIPK=KIPK×VEA, while the relationship between the fSW and VEA in PFM is that: fSW=fMAX−Δf×(VEA|MAX−VEA), wherein, fMAX and VEA|MAX are respectively the highest frequency of the constant voltage control and the amplified error value corresponding to the highest frequency. The relationship between the static error (the difference between the output voltage and the preset reference voltage) and the output current is shown in FIG. 1. Along with the increase of the output current IOUT (namely, the increase of the load), VIPK or fSW increases, namely, VEA increases, that is, the static error increases.
FIG. 2 is a block diagram illustrating the structure of the power control circuit with constant output voltage compensation in the prior art. The control structure includes a resistor R1, a resistor R2, a CV loop control module 101, a controllable current source S1, a driving module 2, a power transistor M1, and a resistor Rs. The connection relationship between the elements is as follows: a first end of the resistor R1 is connected to the primary-side feedback source N*VOUT of the output voltage; a second end of the resistor R1 and a first end of the resistor R2 are connected to the pin FB of the control chip of the power supply and are further connected to a first input end of the CV loop control module 101 and an output end of the controllable current source S1; a second end of the resistor R2 is connected to the power supply ground; a first output end of the CV loop control module 101 is connected to a control end of the controllable current source S1; an input end of the controllable current source S1 is connected to the power supply signal terminal Vsupply of the chip; a second output end of the CV loop control module 101 is connected to the input end of the driving module 2; an output end of the driving module 2 is connected to the grid of the power transistor M1; a drain of the power transistor M1 is connected to a pin SW of the chip; the source of the power transistor M1 is connected to a first end of the resistor Rs and further connected to the pin CS of the chip; a second end of the resistor Rs is connected to the power supply ground. The working principle is as follows: the CV loop control module 101 detects the magnitude of the output load, and controls the current of the controllable current source S1 based on the magnitude of the detected output load. Further, one flow of current ICABLE, which has a negative correlation with the output load, flows out of the chip from the pin FB. The feedback voltage is represented as
      V    FB    =      N    *          V      OUT        *                            R          2                                      R            1                    +                      R            2                              .      As the current ICABLE flows through the resistor R2, the voltage VFB increases by ICABLE*R2, which makes the voltage VEA reduce by ICABLE*R2*AV, and the output voltage VOUT of the power supply output stage module 3 reduces as well. Along with the decrease of the output current IOUT (namely the decrease of the load), the voltage VEA decreases, and the current ICABLE increases gradually. For larger current ICABLE, the voltage VFB increases more, and the voltage VOUT reduces much more than that without compensation. With reference to the relationship between the static error of the output voltage and the output load shown in FIG. 1, it can be seen that the precision of the constant output voltage is improved.
FIGS. 3(a) and 3(b) illustrate waves corresponding to the compensation method for constant output voltage in the prior art. As shown in FIG. 3b), the load increases from zero load to full load, and the output voltage without compensation decreases from a higher value to a lower value. As can be seen from FIG. 2, the compensation current ICABLE increases along with the reduction of the load. In the interval of light load or even no load, a larger current flows from the power supplying module, which increases the standby power dissipation of the power supply system. As shown in FIG. 3a), P1 represents the standby power dissipation when no output compensation is applied; P2 represents the standby power dissipation when output compensation is applied; PCABLE is the increased value. As the compensation current is larger, PCABLE is larger, as a result the standby power dissipation is likely to be larger than the required value PDEMAND. What's more, in order to achieve better properties of power supply, such as higher efficiency and better utilization of the transformer, a control policy relevant to the input voltage is introduced in the CV control loop, which makes the modulation gain of the CV loop (the correspondence between the detected output load and the actual output load of the CV loop) differs between conditions of high input voltages and conditions of low input voltages. When the same profile of the compensation current ICABLE is applied, different output voltage compensation effects are attained. As shown in the figure, there are remarkable differences between the output voltage curve High line (solid) and the output voltage curve Low line (dotted), which influences the precision of the output voltage. The above situations influence the properties of the power supply converter from different aspects. As it is desirable to avoid the above situations through design of the circuit, the traditional compensation methods for constant output voltage should be adjusted.